The consumer market demand for semiconductor devices with enhanced performance, more diverse functionality and improved reliability has driven technological innovations in all involved technical fields. This is also true for the areas of packaging and assembly which constitute the last phase of single or multiple chip fabrication. Packaging provides the necessary interconnects between a chip and a chip carrier as well as a protective enclosure of the assembly protecting it against chemical or mechanical damage.
The occurrence of thermo-mechanically induced stress defects in packaged components is a critical problem impacting the lifetime of electronic devices. Delamination or crack formations at device interfaces or solder joint failures are typical issues for these devices.